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SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 1 ordering information part numbers description device vendor sg2567rd312893hbd 256mx72 (2gb), ddr3, 240-pin registered dimm, parity, ecc, 128mx8 based, pc3-10600, ddr3-1333-999, 30.00mm, green module (rohs compliant). hynix, rev. b h5tq1g83bfr-h9c sg2567rd312893sdd 256mx72 (2gb), ddr3, 240-pin registered dimm, parity, ecc, 128mx8 based, pc3-10600, ddr3-1333-999, 30.00mm, green module (rohs compliant). samsung, rev. d k4b1g0846d-hch9 sg2567rd312893sed 256mx72 (2gb), ddr3, 240-pin registered dimm, parity, ecc, 128mx8 based, pc3-10600, ddr3-1333-999, 30.00mm, green module (rohs compliant). samsung, rev. e k4b1g0846e-hch9 (all specifications of this module are subject to change without notice.)
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 2 revision history ? february 20, 2009 datasheet released.
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 3 2gbyte (256mx72) ddr3 sdram module - 128mx8 based 240-pin dimm, registered, parity, ecc features ? standard = jedec ? configuration = ecc ? number of module ranks = 2 ? number of devices = 18 ?v dd = v ddq = 1.5v ?v ddspd = 1.7v to 3.6v ? cycle time = 1.5ns ?cas latency = 6, 8, 9 ? additive latency = 0, cl-1, and cl-2 ?cas write latency (cwl) = 5, 6, 7 ? burst length = bc4, bl8, bc4 or bl8 (on the fly) ? burst length = nibble sequential & interleave mode ? internal banks per sdram = 8 ? refresh = 8k/64ms ? device package = fbga ? lead finish = gold ? length x height = 133.35mm x 30.00mm ? no. of sides = double-sided ? mating connector (examples) vertical = amp - 5-1932000-9 ? zq calibration supported ? on chip dll align dq, dqs and dqs transition with ck transition ? dm write data-in at both the rising and falling edges of the data strobe ? all addresses and control inputs latched on the rising edges of the clock ? dynamic on die termination supported ? driver strength selected by emrs ? asynchronous reset pin supported ? write levelization supported ? 8-bit pre-fetch pin description table symbol type polarity function ck0~ck1, ck0 ~ck1 input differential crossing ck and ck are differential clock inputs. all the ddr3 sdram address/control inputs are sam- pled on the crossing of the positive edge of ck and the negative edge of ck . output (read) data is referenced to the crossing of ck and ck (both directions of crossing). cke0, cke1 input active high activates the sdram ck signal when high and deactivates the ck signal when low. by deacti- vating the clocks, cke low initiates the power down mode, or the self refresh mode. cs0 ~cs1 input active low enables the associated sdram command decoder when low and disables the command decoder when high. when decoder is disabled, new commands are ignored but previous opera- tions continue.this signal provides for external rank selection on systems with multiple ranks. odt0, odt1 input active high when high, termination resistance is enabled for all dq, dqs, dqs and dm pins, assuming this function is enabled on the dram. ba0~ba2 input - selects which sdram bank of the eight is activated. addressing device configuration 128mx8 number of internal banks 8 bank address ba0 - ba2 auto precharge a10/ap bc switch on the fly a12/bc row address a0 - a13 column address a0 - a9
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 4 pin description table (contd.) symbol type polarity function a0~a15 input - during a bank activate command cycle, address inputs define the row address (ra0?ra13). during a read or write command cycle, address inputs define the column address (ca0?ca9). in addition to the column address, ap is used to invoke auto-precharge operation at the end of the burst read or write cycle. if ap is high, auto-precharge is selected and ba0, ba1, ba2 defines the bank to be precharged. if ap is low, auto-precharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0, ba1, ba2 to control which bank(s) to pre- charge. if ap is high, all banks will be precharged regardles s of the state of ba0, ba1 or ba2. if ap is low, ba0, ba1 and ba2 are used to define which bank to precharge. a12(bc ) is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed (high, no burst chop; low, burst chopped). a14 & a15 are only connected to the register for the parity check. ras , cas , we input active low ras , cas , and we (along with cs ) define the command being entered. dq0~dq63 cb0~cb7 input/ output - data and check bit input/output pins. dqs0~dqs8 dqs0 ~dqs8 input/ output differential crossing data strobe for input and output data. dm0~dm8 input active high dm is an input mask signal for write data. input data is masked when dm is sampled high coinci- dent with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. par_in input active high parity bit for the address and control bus. (?1 ?: odd, ?0 ?: even) err_out output active low parity error detected on the address and control bus. a resistor may be connected from err_out bus line to v dd on the system planar to act as a pull up. sa0~sa2 input - these signals are tied at the system to either v ss or v ddspd to configure the serial spd eeprom address range. sda input/ output - this bidirectional pin is used to transfer data into or out of the spd eeprom. an external resis- tor may be connected from the sda bus line to v ddspd to act as a pullup on the system board. scl input - this signal is used to clock data into and out of the spd eeprom. an external resistor may be connected from the scl bus tied to v ddspd to act as a pullup on the system board. event output active low this signal indicates that a thermal event has been detected in the thermal sensing device.the system should guarantee the electrical level requirement is met for the event pin on ts/spd part. no pull-up resister is provided on dimm. reset input active low asynchronous reset is active when reset is low, and inactive when reset is high. reset must be high during normal operation. reset is cmos rail to rail signal with dc high and low at 80% and 20% of v dd . v dd, v ss supply - power and ground for the ddr3 sdram input buffers, and core logic. v dd and v ddq pins are tied to v dd /v ddq planes on these modules. v ss pins are tied to v ss planes on these modules. v ddq supply - power supply for the ddr3 sdram output buffers to provide improved noise immunity. v ddq shares the same power plane as v dd pins. v refdq supply reference voltage for i/o inputs. v refca supply - reference voltage for address/command inputs. v ddspd supply - power supply for spd eeprom. this supply is separate from the v dd /v ddq power plane. v tt supply - termination voltage for address/command/control/clock nets. nc - - no connect.
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 5 ddr3 240-pin dimm pin list pin no pin name pin no pin name pin no pin name pin no pin name pin no pin name pin no pin name pin no pin name pin no pin name 1 v refdq 31 dq25 61 a2 91 dq41 121 v ss 151 v ss 181 a1 211 v ss 2 v ss 32 v ss 62 v dd 92 v ss 122 dq4 152 dm3 182 v dd 212 dm5 3dq0 33dqs3 63 ck1 93 dqs5 123 dq5 153 nc 183 v dd 213 nc 4 dq1 34 dqs3 64 ck1 94 dqs5 124 v ss 154 v ss 184 ck0 214 v ss 5 v ss 35 v ss 65 v dd 95 v ss 125 dm0 155 dq30 185 ck0 215 dq46 6dqs0 36 dq26 66 v dd 96 dq42 126 nc 156 dq31 186 v dd 216 dq47 7 dqs0 37 dq27 67 v refca 97 dq43 127 v ss 157 v ss 187 event 217 v ss 8 v ss 38 v ss 68 par_in 98 v ss 128 dq6 158 cb4 188 a0 218 dq52 9dq2 39cb0 69 v dd 99 dq48 129 dq7 159 cb5 189 v dd 219 dq53 10 dq3 40 cb1 70 a10/ap 100 dq49 130 v ss 160 v ss 190 ba1 220 v ss 11 v ss 41 v ss 71 ba0 101 v ss 131 dq12 161 dm8 191 v dd 221 dm6 12 dq8 42 dqs8 72 v dd 102 dqs6 132 dq13 162 nc 192 ras 222 nc 13 dq9 43 dqs8 73 we 103 dqs6 133 v ss 163 v ss 193 cs0 223 v ss 14 v ss 44 v ss 74 cas 104 v ss 134 dm1 164 cb6 194 v dd 224 dq54 15 dqs1 45 cb2 75 v dd 105 dq50 135 nc 165 cb7 195 odt0 225 dq55 16 dqs1 46 cb3 76 cs1 106 dq51 136 v ss 166 v ss 196 a13 226 v ss 17 v ss 47 v ss 77 odt1 107 v ss 137 dq14 167 nc 197 v dd 227 dq60 18 dq10 48 nc 78 v dd 108 dq56 138 dq15 168 reset 198 cs3 (nc) 228 dq61 19 dq11 49 nc 79 cs2 (nc) 109 dq57 139 v ss 169 cke1 199 v ss 229 v ss 20 v ss 50 cke0 80 v ss 110 v ss 140 dq20 170 v dd 200 dq36 230 dm7 21 dq16 51 v dd 81 dq32 111 dqs7 141 dq21 171 a15 201 dq37 231 nc 22 dq17 52 ba2 82 dq33 112 dqs7 142 v ss 172 a14 202 v ss 232 v ss 23 v ss 53 err_out 83 v ss 113 v ss 143 dm2 173 v dd 203 dm4 233 dq62 24 dqs2 54 v dd 84 dqs4 114 dq58 144 nc 174 a12/bc 204 nc 234 dq63 25 dqs2 55 a11 85 dqs4 115 dq59 145 v ss 175 a9 205 v ss 235 v ss 26 v ss 56 a7 86 v ss 116 v ss 146 dq22 176 v dd 206 dq38 236 v ddspd 27 dq18 57 v dd 87 dq34 117 sa0 147 dq23 177 a8 207 dq39 237 sa1 28 dq19 58 a5 88 dq35 118 scl 148 v ss 178 a6 208 v ss 238 sda 29 v ss 59 a4 89 v ss 119 sa2 149 dq28 179 v dd 209 dq44 239 v ss 30 dq24 60 v dd 90 dq40 120 v tt 150 dq29 180 a3 210 dq45 240 v tt
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 6 rcs0 rcs1 rcke0 rcke1 rodt0 rodt1 block diagram dqs s cke odt dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 zq dqs0 dqs0 dm0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u1 note: unless otherwise noted, data resistor values are 15 5%. 240 dqs s cke odt dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 zq u10 240 dqs s cke odt dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 zq dqs4 dqs4 dm4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 u5 240 dqs s cke odt dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 zq u14 240 dqs s cke odt dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 zq dqs1 dqs1 dm1 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 u2 240 dqs s cke odt dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 zq u11 240 dqs s cke odt dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 zq dqs5 dqs5 dm5 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 u6 240 dqs s cke odt dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 zq u15 240 dqs s cke odt dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 zq dqs2 dqs2 dm2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 u3 240 dqs s cke odt dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 zq u12 240 dqs s cke odt dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 zq dqs6 dqs6 dm6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 u7 240 dqs s cke odt dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 zq u16 240 dqs s cke odt dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 zq dqs3 dqs3 dm3 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u4 240 dqs s cke odt dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 zq u13 240 dqs s cke odt dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 zq dqs7 dqs7 dm7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 u8 240 dqs s cke odt dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 zq u17 240 dqs s cke odt dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 zq dqs8 dqs8 dm8 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 u9 240 dqs s cke odt dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 zq u18 240
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 7 event scl sda sa0 sa1 sa2 r e g i s t e r / p l l (x1) notes: 1. each address, command and control signal output line from the register is terminated at the end of the line through a 39 series resistor to v tt . 2. data bits may be swapped within a device. however, dq/dqs/dm relationship must be maintained as shown on page 6. v ddspd v dd /v ddq v tt v refca v refdq v ss u20 u1-u18, u21 u1-u18, u21 u1-u18, u21 u1-u18 u1-u18, u21 pck pck 120 a0~a15 ba0~ba2 ras cas we cs0 cs1 odt0 odt1 cke0 cke1 reset par_in ck0 ck0 ra0~ra13 to all devices (u1-u18) rba0~rba2 to all devices (u1-u18) rras to all devices (u1-u18) rcas to all devices (u1-u18) rwe to all devices (u1-u18) rcs0 to s on (u1-u9) rcs1 to s on (u10-u18) rodt0 to odt on (u1-u9) rodt1 to odt on (u10-u18) rcke0 to cke on (u1-u9) rcke1 to cke on (u10-u18) reset to all devices (u1-18) err_out to pin 53 of the connector pck to ck on (u1-18) pck to ck on (u1-18) 22 u21 v dd scl sda sa0 sa1 sa2 v ddspd event spd eeprom with u20 120 22 75 ck1 ck1 120 thermal sensor
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 8 physical dimensions 240-pin dimm module (all dimensions are in millimeters with 0.15mm tolerance unless specified otherwise.) 64 5.00 full r 3.80 2.50 1.500.10 0.800.05 1.00 2.500.20 0.200.15 65 detail c detail b detail a r0.70 (8x) 2.10 (4x) 3.00 (2x) 5.175 47.00 71.00 5.175 3.77 (max.) 30.00 133.350.15 15.80 17.30 9.50 front view 5.00 detail a detail b detail c 1.270.10 back view 1 120 48 49 121 240 168 169 ? 2.50 (2x) 2.20 (2x) 2.30 (2x) 5.175 5.175 5.00 side view 4.00 (min) detail d (2x) 60 15 detail d 14.9 (4x) r0.75 (8x) r0.75 (4x) 3.00 (4x) 1.20 (2x) 0.1250.075 (2x) 0.1250.075 (2x)
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 9 serial presence detect table (sg2567rd312893hbd/sdd/sed) byte no. byte description value supported hex value 0 no. of bytes used, no. of bytes in spd device, crc coverage 176, 256, 0~116 92h 1 spd revision revision 1.0 10h 2 key byte/dram device type ddr3 sdram 0bh 3 key byte/module type rdimm 01h 4 sdram density and banks 1gb, 8 banks 02h 5 sdram addressing 14 rows, 10 columns 11h 6 reserved - 00h 7 module organization 2 ranks, x8 09h 8 module memory bus width x72 0bh 9 fine timebase (ftb) dividend/divisor 2.5ps 52h 10 medium timebase dividend 1 01h 11 medium timebase divisor 8 08h 12 minimum sdram cycle time (t ck min) 1.5ns 0ch 13 reserved - 00h 14 cas latencies supported (cl4-cl11) 6, 8, 9 34h 15 cas latencies supported (cl12-cl18) - 00h 16 minimum cas latency time (t aa min) 13.5ns 6ch 17 minimum write recovery time (t wr min) 15ns 78h 18 minimum ras to cas delay time (t rcd min) 13.5ns 6ch 19 minimum row active to row active delay time (t rrd- min) 6ns 30h 20 minimum row precharge delay time (t rp min) 13.5ns 6ch 21 upper nibbles for t ras and t rc -11h 22 minimum active to precharge delay time (t ras min) 36ns 20h 23 minimum active to active/refresh delay time (t rc- min) 49.5ns 8ch 24 minimum refresh recovery delay time (t rfc min) (lsb) 110ns 70h 25 minimum refresh recovery delay time (t rfc min) (msb) 110ns 03h
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 10 serial presence detect table (contd.) byte no. byte description value supported hex value 26 minimum internal write to read command delay time (t wtr min) 7.5ns 3ch 27 minimum internal read to precharge command delay time (t rtp min) 7.5ns 3ch 28 upper nibble for t faw 30ns 00h 29 minimum four active window delay time (t faw ) 30ns f0h 30 sdram output drivers supported dll-off mode, rzq/7, rzq/6 83h 31 sdram thermal and refresh options asr, ext. temp. range 05h 32 module thermal sensor eeprom with thermal sensor 80h 33 sdram device type monolithic 00h 34~59 reserved - 00h 60 module nominal height 30mm 0fh 61 module maximum thickness double-sided 11h 62 reference raw card used r/c b, rev. 0 01h 63 dimm module attributes 1 row, 1 register 05h 64 rdimm thermal heat spreader none 00h 65 register manufacturer id code (lsb) generic 00h 66 register manufacturer id code (msb) generic 00h 67 register revision number - ffh 68 register type sste32882 00h 69 rc1 (ms nibble) / rc0 (ms nibble) raw card b 01h 70 rc3 (ms nibble) / rc2 (ms nibble) raw card b 00h 71 rc5 (ms nibble) / rc4 (ms nibble) raw card b 00h 72 rc7 (ms nibble) / rc6 (ms nibble) raw card b 00h 73 rc9 (ms nibble) / rc8 (ms nibble) raw card b 00h 74 rc11 (ms nibble) / rc10 (ms nibble) raw card b 00h 75 rc13 (ms nibble) / rc12 (ms nibble) raw card b 00h 76 rc15 (ms nibble) / rc14 (ms nibble) raw card b 00h 77~116 reserved - 00h
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 11 serial presence detect table (contd.) note: 1. manufacturing location: 00h - undefined, 01h - fremont, usa, 02h - aguada, puerto rico, 03h - east kilbride, scotland, 04h - penang, malaysia, 05h - bangalore, india, 06h - sao paulo, brazil, 07h - aguadilla, puerto rico, 08h - mayaguez, puerto rico, 09h - santo domingo, dominican republic, 0ah - dongguan, china, byte no. byte description value supported hex value 117 module manufacturer id code (lsb) continuation code 01h 118 module manufacturer id code (msb) smart id code 94h 119 module manufacturing location see note 1 01h 120 module manufacturing date (year) date date 121 module manufacturing date (week) date date 122~125 module serial number serial number s. no 126 spd cyclical redundancy code 22h 127 spd cyclical redundancy code c7h 128~145 module part number SG2567RD312893UUD 146 module revision code (spd revision) revision 0 00h 147 module revision code - 00h 148 dram manufacturer id code (lsb) hynix samsung 80h 80h 149 dram manufacturer id code (msb) hynix samsung adh ceh 150~175 manufacturer specific data smart modular technologies 176~255 open for customer use - 00h
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 12 a7 mode 0normal 1test mode register (mr0) table definition the mode register stores the data for controlling the various operating modes of ddr3 sdram. it controls cas latency, burst length, burst chop, burst sequence, test mode, dll reset, t wr and various vendor specific options to make ddr3 sdram use- ful for various applications. the mode register is written by asserting low on cs , ras , cas , we , ba0, ba1 and ba2 while con- trolling the state of address pins a0~a15. ba2 ba1 ba0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 1 00 0 1 0 1 0 1 ppd wr dll tm cas latency rbt cl bl mode register 0 a8 dll reset 0no 1yes a1 a0 burst length 00 8 (fixed) 01 bc4 or 8 (on-the-fly) 1 0 bc4 (fixed) 11 reserved a6 a5 a4 a2 cas latency 0000 reserved 0010 5 (optional) 0100 6 0110 7 (optional) 1000 8 (optional) 1010 9 (optional) 1100 10 (optional) 1110 11 (optional) a11 a10 a9 wr (cycles) 000 reserved 001 5 2 010 6 2 011 7 2 100 8 2 101 10 2 110 12 2 111 reserved a3 read burst type 0 nibble sequential 1 interleave a12 dll control for precharge pd 0 slow exit (dll off) 1 fast exit (dll on) ba1 ba0 mr select 00 mr0 01 mr1 10 mr2 11 mr3 notes: 1. ba2 and a13~a15 are reserved for future use and must be programmed to 0 during mrs. 2. wr(write recovery for autoprecharge)min in clock cycles is calculated by dividing t wr (in ns) by t ck (in ns) and rounding up to the next inte- ger: wrmin[cycles] = round-up(twr[ns] / tck[ns]). the wr value in the mode register must be program med to be equal or larger th an wrmin. the programmed wr value is used with t rp to determine t dal .
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 13 a7 write leveling enable 0 disabled 1 enabled mode register (mr1) table definition the mode registers mr1 stores the data for enabling or disabling the dll, output driver strength, rtt_nom impedance, addi- tive latency, write leveling enable, tdqs enable and qoff. the mode register 1 is written by asserting low on cs , ras , cas , we , high on ba0 and low on ba1 and ba2, while controlling the state of address pins a0~a15. ba2 ba1 ba0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 1 01 0 1 0 1 0 1 qoff tdqs 0 1 rtt_nom 0 1 level rtt_nom d.i.c al rtt_nom d.i.c dll mode register 1 a11 tqds enable 0 disabled 1 enabled a0 dll enable 0 enable 1 disable note: rzq = 240 a5 a1 output driver impedance control 0 0 reserved for rzq/6 01 rzq/7 10 rzq/tbd 11 rzq/tbd note: rzq = 240 a9 a6 a2 rtt_nom 3 0 0 0 odt disabled 001 rzq/4 010 rzq/2 011 rzq/6 100 rzq/12 4 101 rzq/8 4 1 1 0 reserved 1 1 1 reserved a4 a3 additive latency 0 0 0 (al disabled) 01cl-1 10cl-2 11reserved a12 qoff 2 0 output buffer enabled 1 output buffer disabled notes: 1. ba2 and a8, a10, a13~a15 are reserved for future use and must be programmed to 0 during mrs. 2. outputs disabled - dqs, dqss, dqs s. 3. in write leveling mode (mr1[bit7] = 1) with mr1[bit12] = 1, all rtt_nom settings are allowed; in write leveling mode (mr1[bit 7] =1) with mr1[bit12] = 0, only rtt_nom settings of rzq/2, rzq/4 and rzq/6 are allowed. 4. if rtt_nom is used during writes, only the values rzq/2, rzq/4 and rzq/6 are allowed. ba1 ba0 mr select 00 mr0 01 mr1 10 mr2 11 mr3
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 14 mode register (mr2) table definition the mode registers mr2 stores the data for controlling refresh related features, rtt_wr impedance, and cas write latency. the mode register 2 is written by asserting low on cs , ras , cas , we , high on ba1 and low on ba0 and ba2 while controlling the state of address pins a0~a15. ba2 ba1 ba0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 1 10 0 1 0 1 0 1 0 1 0 1 rtt_wr 0 1 srt asr cwl pasr mode register 2 a6 auto self-refresh (asr) 0 manual sr ref. (srt) 1 asr enable (optional) a2 a1 a0 partial array self-refresh (optional) 0 0 0 full array 0 0 1 half array (ba[2:0] = 000, 001, 010, & 011) 0 1 0 quarter array (ba[2:0] = 000 & 001) 0 1 1 1/8th array (ba[2:0] = 000) 1 0 0 3/4 array (ba[2:0] = 010,011,100,101,110, & 111) 1 0 1 half array (ba[2:0] = 100, 101, 110, & 111) 1 1 0 quarter array (ba[2:0] = 110, & 111) 1 1 1 1/8th array (ba[2:0] = 111) a5 a4 a3 cas write latency 000 5 (t ck 2.5ns) 0 0 1 6 (2.5ns > t ck 1.875ns) 0 1 0 7 (1.875ns > t ck 1.5ns) 0118 (1.5ns > t ck 1.25ns) 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved a10 a9 rtt_wr 2 0 0 dynamic odt off 0 1 rzq/4 1 0 rzq/2 11reserved a7 self-refresh temperature (srt) range 0 normal operating temperature range 1 extended (optional) operating temperature range notes: 1. ba2, a8 and a11~a15 are reserved for future use and must be programmed to 0 during mrs. 2. if rtt_wr value can be applied during writes even when rtt_nom is disabled. during write leveling, dynamic odt is not availab le. ba1 ba0 mr select 00 mr0 01 mr1 10 mr2 11 mr3
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 15 mode register (mr3) table definition the mode register mr3 controls multi-purpose registers. the mode register 3 is written by asserting low on cs , ras , cas , we , high on ba1 and ba0, low on ba2 while controlling the state of address pins a0~a15. ba2 ba1 ba0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 1 11 0 1 mpr mpr loc mode register 3 mpr address a2 mpr 0 normal operation 3 1 dataflow from mpr mpr address a1 a0 mpr location 00 predefined pattern 2 01 rfu 10 rfu 11 rfu notes: 1. ba2, a3~a15 are reserved for future use and must be programmed to 0 during mrs. 2. the predefined pattern will be used for read synchronization. 3. when mpr control is set for normal operation (mr3 a[2] = 0), then mr3 a[1:0] will be ignored. ba1 ba0 mr select 00 mr0 01 mr1 10 mr2 11 mr3
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 16 command truth table the following truth tables provide a general reference of available commands. for a more detailed description please refer to the device data sheets. (a) notes 1- 4 apply to the entire command truth table. (b) note 5 applies to all read/write command. [ba= bank address, ra= row address, ca = column address, bc = burst chop, x = don?t care, v = valid] function abbrevi ation cke cs ras cas we ba0~ ba2 a13~ a15 a12/ bc a10/ ap a0-a9, a11 notes previous cycle current cycle mode register set mrs h h llllba op code refresh ref h h l l lhvvvv v self-refresh entry sre h l l l lhvvvv v7, 9, 12 self-refresh exit srx l h hvvv vvvv v 7, 8, 9, 12 lhhh single bank precharge pre h h l l h l ba v v l v precharge all banks prea h h l l h l v v v h v bank activate act h h l l h h ba row address write (fixed bl8 or bc4) wr h h l h l l ba rfu v l ca write (bc4, on the fly) wrs4 h h l h l l ba rfu l l ca write (bl8, on the fly) wrs8 h h l h l l ba rfu h l ca write with auto-precharge (fixed bl8 or bc4) wra h h l h l l ba rfu v h ca write with auto-precharge (bc4, on the fly) wras4 h h l h l l ba rfu l h ca write with auto-precharge (bl8, on the fly) wras8 h h l h l l ba rfu h h ca read (fixed bl8 or bc4) rd h h l h l h ba rfu v l ca read (bc4, on the fly) rds4 h h l h l h ba rfu l l ca read (bl8, on the fly) rds8 h h l h l h ba rfu h l ca read with auto-precharge (fixed bl8 or bc4) rda h h l h l h ba rfu v h ca read with auto-precharge (bc4, on the fly) rdas4h h lhlhbarfulhca read with auto-precharge (bl8, on the fly) rdas8h h lhlhbarfuhhca no operation nop h h lhhhvvvv v10 device deselected des h h hxxxxxxx x11 power-down entry pde h l lhhh vvvv v6, 12 hvvv power-down exit pdx l h lhhh vvvv v6, 12 hvvv zq calibration long zqcl h h l h h l x x x h x zq calibration short zqcs h h l h h l x x x l x
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 17 command truth table notes: 1. all ddr3 sdram commands ar e defined by states of cs , ras , cas , we , and cke at the rising edge of the clock. the msb of ba, ra and ca are device density and configuration dependant. 2. reset command is enabled when low, which will be used only for asynchronous reset, so reset must be maintained high during any function. 3. bank addresses (ba) determine which bank is to be operated upon. for (e)mrs, ba selects an (extended) mode register. 4. ?v? means ?h or l (but a defined logic level)? and ?x? means either ?defined or undefined (like floating) logic level?. 5. burst reads or writes cannot be terminated or inte rrupted and fixed/on-the-fly bl will be defined by the mrs. 6. the power-down mode does not perform any refresh operation. 7. the state of odt does not affect the states described in this table. the odt function is not available during self-refresh. 8. self-refresh exit is asynchronous. 9. v ref (both v refdq and v refca ) must be maintained during self-refresh operation. 10. the no operation command should be used in cases when the ddr3 sdram is in an idle or wait state. the purpose of the no oper ation command (nop) is to prevent the ddr3 sdram from registerin g any unwanted commands between operations. a no operation com- mand will not terminate a previous operation that is sti ll executing, such as a burst read and write cycle. 11. the deselect command performs the same function as no operation command. 12. refer to the cke truth table for more detail with cke transition.
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 18 cke truth table (a) notes 1-7 apply to the entire cke truth table. (b) cke low is allowed only if tmrd and tmod are satisfied. notes: 1. cke (n) is the logic state of cke at clock edge n; cke (n-1) was the state of cke at the previous clock edge. 2. current state is defined as the state of the ddr3 sdram immediately prior to clock edge n. 3. command (n) is the command registered at clock edge n, and action (n) is a result of command (n), odt is not included here. 4. all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. the state of odt does not affect the states described in this table. the odt function is not available during self-refresh. 6. cke must be registered with the same value on t cke min consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the t cke min clocks of registration. thus, after any cke trans ition, cke may not transition from its valid level during the time period of t is + t cke min + t ih . 7. deselect and nop are defined in the command truth table. 8. on self-refresh exit, deselect or nop commands must be issued on every clock edge occurring during the t xs period. read or odt commands may be issued only after t xsdll is satisfied. 9. self-refresh mode can only be entered from the all banks idle state. 10. must be a legal command as defined in the command truth table. 11. valid commands for power-down entry and exit are nop and deselect only. 12. valid commands for self-refresh exit are nop and deselect only. 13. self-refresh can not be entered during read or write operations. 14. the power-down does not perform any refresh operations. 15. ?x? means ?don?t care? (including floating around v ref ) in self-refresh and power-down. it also applies to address pins. 16. v ref (both v refdq and v refca ) must be maintained during self-refresh operation. 17. if all banks are closed at the conclusion of the read, write or precharge command, then prechar ge power-down is entered, oth erwise active power-down is entered. 18. ?idle state? is defined as all banks are closed (t rp , t dal , etc. satisfied), no data bursts are in progress, cke is high, and all timings from previous operations are satisfied (t mrd , t mod , t rfc , t zqinit , t zqoper , t zqcs , etc.) as well as all self-refresh exit and power-down exit parameters are satisfied (t xs , t xp , t xpdll , etc.). current state cke command (n) 3 ras , cas , we , cs action (n) 3 notes previous cycle (n-1) current cycle (n) power-down l l x maintain power-down 14, 15 l h deselect or nop power-down exit 11, 14 self-refresh l l x maintain self-refresh 15, 16 l h deselect or nop self-refresh exit 8, 12, 16 bank activate h l deselect or nop active power-down entry 11, 13, 14 reading h l deselect or nop power-down entry 11, 13, 14, 17 writing h l deselect or nop power-down entry 11, 13, 14, 17 precharging h l deselect or nop power-down entry 11, 13, 14, 17 refreshing h l deselect or nop precharge power-down entry 11 all banks idle h l deselect or nop precharge power-down entry 11, 13, 14, 18 l refresh self-refresh 9, 13, 18 for more details with all signals, see command truth table on the previous pages. 10
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 19 absolute maximum dc ratings notes: 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. 3. v dd and v ddq must be within 300 mv of each other at all times and v ref must be not greater than 0.6*v ddq . when v dd and v ddq are less than 500 mv; v ref may be equal to or less than 300 mv. symbol parameter rating units notes v dd voltage on v dd relative to v ss -0.4 ~ 1.975 v 1, 3 v ddq voltage on v ddq relative to v ss -0.4 ~ 1.975 v 1, 3 v in, v out voltage on any pin relative to v ss -0.4 ~ 1.975 v 1 v ddspd voltage on v ddspd relative to v ss 1.7 ~ 3.6 v 1 t stg storage temperature -50 to +100 c 1, 2 absolute maximum ratings operating temperature range notes: 1. operating temperature t oper is the case surface temperature on the center/top side of the dram. 2. the normal temperature range specifies the temperatures where all dram specifications will be supported. during operation, the dram case temperature must be maintained between 0c and 85c under all operating conditions. 3. some applications require operation of the dram in the extended temperature range between 85c and 95c case temperature. full specifications are supported in this range, but the following additional conditions apply: a) refresh commands must be doubled in frequency, therefore reducing the refresh interval t refi to 3.9 s. it is also possible to specify a component with 1x refresh (t refi to 7.8 s) in the extended tem- perature range. please refer to the spd for option availability. b) if self-refresh operation is required in the extended temperature range, then it is mandatory to either use the manual self-refresh mode with extended temperature range capability (mr2 a6 = 0b and mr2 a7 = 1b) or enable the optional auto self-refresh mode (mr2 a6 = 1b and mr2 a7 = 0b). please refer to the spd for option availability. symbol parameter max units notes t oper normal operating temperature range (case) 0 to 85 c 1, 2 extended operating temperature range (optional) 85 to 95 c 1, 3
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 20 recommended dc operating conditions notes: 1. under all conditions, v ddq must be less than or equal to v dd . 2. v ddq tracks with v dd . ac parameters are measured with v dd and v ddq tied together. 3. v tt = v ddq /2 symbol parameter rating units notes min typ max v dd supply voltage 1.425 1.5 1.575 v 1, 2 v ddq supply voltage for output 1.425 1.5 1.575 v 1 v ddspd spd supply voltage 3.0 3.3 3.6 v v tt spd supply voltage 0.7125 0.75 0.7875 v 3 v ss ground 0 0 0 v ac and dc logic input levels for single-ended signals notes: 1. for dq and dm, v ref = v refdq . for input only pins except reset#, v ref = v refca . 2. the ac peak noise on v ref may not allow v ref to deviate from v ref(dc) by more than 1% v dd (for refer- ence: approx. 15mv). 3. for reference: approx. v dd /2 15mv. symbol parameter ddr3-1333 units notes min max v ih(dc) dc input logic high v ref + 0.100 v dd v1 v il(dc) dc input logic low v ss v ref - 0.100 v1 v ih(ac) ac input logic high v ref + 0.175 -v1 v il(ac) ac input logic low - v ref - 0.175 v1
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 21 differential swing requirements for clock (ck/ck ) and strobe (dqs/dqs ) notes: 1. used to define a differential signal slew-rate. 2. for ck/ck , use v ih /v il(ac) of add/cmd and v refca ; for dqs/dqs , use v ih /v il(ac) of dqs and v refdq ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. these values are not defined, however the single-ended signals ck, ck , dqs, dqs need to be within the respective limits (v ih(dc) max, v il(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. symbol parameter ddr3-1333 units notes min max v ihdiff differential input logic high 0.200 note 3 v 1 v ildiff differential input logic high note 3 -0.200 v 1 v ihdiff(ac) ac input logic high 2 * (v ih(ac) - v ref ) note 3 v 2 v ildiff(ac) ac input logic low note 3 2 * (v ref - v il(ac) ) v2 single-ended input slew rate definition description measured defined by applicable for from to input slew rate for rising edge v ref v il(ac)min setup (t is , t ds ) input slew rate for falling edge v ref v il(ac)max input slew rate for rising edge v il(dc)max v ref hold (t ih , t dh ) input slew rate for falling edge v il(dc)min v ref v ih ac () min v ref ? trs --------------------------------------------------------- - v ref v il ac () max ? tfs ---------------------------------------------------------- v ref v il dc () max ? tfh ---------------------------------------------------------- - v ih dc () min v ref ? trh ----------------------------------------------------------
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 22 input/output capacitance notes: 1. although the dm, tdqs and tdqs pins have different functions, the loading matches dq and dqs. 2. this parameter is not subject to production test. it is verified by design and characterization. 3. absolute value of c ck - c ck 4. absolute value of c io (dqs) - c io (dqs ) 5. ci applies to odt, cs , cke, a0-a15, ba0-ba2, ras , cas , we . 6. c di = c i - 0.5 * (c i (ck) + c i (ck )) 7. c dio = c io (dq,dm) - 0.5 * (c io (dqs) + c io (dqs )) speed bin ddr3-1333 units notes parameter symbol min max input/output capacitance, (dq, dm, dqs, dqs , tdqs, tdqs ) c io 3.0 5 pf 1, 2 input/output capacitance delta, (dq, dm, dqs, dqs , tdqs, tdqs ) c dio -1 0.6 pf 2, 7 input/output capacitance delta, (dqs and dqs ) c ddqs 00.4pf2, 4 input capacitance, (ck and ck ) c ck 2.0 3.0 pf 2 input capacitance delta, (ck and ck ) c dck -0.5pf2, 3 input capacitance, (add, cmd, ctrl input-only pins) c i 1.5 2.5 pf 2, 5 input capacitance delta, (add, cmd, ctrl input-only pins) c di -0.5pf2, 6
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 23 definitions for idd measurement conditions ? low is defined as v in v ilac(max) ; high is defined as v in v ihac(max) . ? stable is defined as inputs are stable at a high or low level. ? floating is defined as inputs are v ref = v ddq / 2. ? read data is defined as the output data switching every clock, and write data is defined as the input data switching every clock, which means that read data and write data are stable during one clock cycle. ? switching is defined by the following table: switching for address, bank address, command signals, data (dq) and data masking (dm) address (row, column): if not otherwise mentioned, the inputs are stable at high or low during 4 clock cycles and then change to the opposite value (e.g. ax ax ax ax ax ax ax ax ax ax ax ax.....) bank address: if not otherwise mentioned, the bank addresses should be switched like the row/column addresses command (cs , ras , cas , we ): define d = {cs , ras , cas , we } = {high, low, low, low} define d = {cs , ras , cas , we } = {high, high, high, high} define command background pattern = d d d d d d d d d d d d ... if other commands are necessary (e.g. act for idd0 or read for idd4r), the background pattern command is substituted by the respective cs , ras , cas , we levels of the neces- sary command. data (dq): data dq is changing between high and low every other data transfer (once per clock) for dq signals, which means that data dq is stable during one clock. data masking (dm): no switching; dm must be driven low at all times. idd timing parameters speed bin ddr3-1333 units parameter 9-9-9 t ckmin (idd) 1.5 ns cl(idd) 9 t rcdmin (idd) 13.5 ns t rcmin (idd) 49.5 ns t rasmin (idd) 36 ns t rpmin (idd) 13.5 ns t faw (idd) 30 ns t rrd (idd) 6ns t rfc (idd) 110 ns
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 24 idd measurement conditions symbol description conditions i dd0 operating current 0 one bank activate precharge cke is high; external clock is on; t ck = t ckmin (idd); t rc = t rcmin (idd); t ras = t rasmin (idd); cs is high between activate and precharge com- mands; command inputs are switching except during activate and precharge commands; row addresses are switching; address input a10 must be low at all times; bank address is fixed (bank 0); data i/o are switching; output buffer (dq/dqs) is off (mr1 bit a12 = 1); rtt_nom and rtt_wr are disabled; bank 0 active in a act-pre loop; all other banks idle. i dd1 operating current 1 one bank activate read precharge cke is high; external clock is on; t ck = t ckmin (idd); t rc = t rcmin (idd); t ras = t rasmin (idd); t rcd = t rcdmin (idd); cl = cl(idd); cs is high between activate, read and precharge commands; command inputs are switching except during activate, read and precharge commands; row addresses are switching; address input a10 must be low at all times; bank address is fixed (bank 0); data i/o are in read data; output buffer (dq, dqs) is off (mr1 bit a12 = 1) in order to achieve i out = 0ma; data i/o should be floating when there is no read data; rtt_nom and rtt_wr are disabled; burst length = 8 fixed (mr0 bits [a1,a0] = {0,0}); bank 0 active in a act-rd-pre loop; all other banks idle. i dd2p (0) precharge power-down current slow exit - mr0 bit a12 = 0 cke is low; external clock is on; t ck = t ckmin (idd); cs is stable; bank addresses, row addresses and command inputs are stable; data inputs are floating; output buffer (dq, dqs) is off (mr1 bit a12 = 1); rtt_nom and rtt_wr are disabled; all banks idle; slow exit (rd and odt commands must satisfy t xpdll-al ) (mr0 bit a12 = 0). i dd2p (1) 1 precharge power-down current fast exit - mr0 bit a12 = 1 cke is low; external clock is on; t ck = t ckmin (idd); cs is stable; bank addresses, row addresses and command inputs are stable; data inputs are floating; output buffer (dq, dqs) is off (mr1 bit a12 = 1); rtt_nom and rtt_wr are disabled; all banks idle; fast exit (any valid command after t xp 2 ) (mr0 bit a12 = 1). i dd2n precharge standby current cke is high; external clock is on; t ck = t ckmin (idd); cs is high; bank addresses, row addresses and command inputs are switching; data inputs are switching; output buffer (dq, dqs) is off (mr1 bit a12 = 1); rtt_nom and rtt_wr are disabled; all banks idle. i dd2q precharge quiet standby current cke is high; external clock is on; t ck = t ckmin (idd); cs is high; bank addresses, row addresses and command inputs are stable; data input are floating; output buffer (dq, dqs) is off (mr1 bit a12 = 1); rtt_nom and rtt_wr are disabled; all banks idle.
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 25 idd measurement conditions (contd.) symbol description conditions i dd3p active power down current 3 always fast exit cke is low; external clock is on; t ck = t ckmin (idd); cs is stable; address and command inputs are stable; data i/o are floating; output buffer (dq, dqs) is off (mr1 bit a12 = 1); rtt_nom and rtt_wr are disabled; all banks active; active power down mode is always ?fast exit? with dll on. i dd3n active standby current cke is high; external clock is on; t ck = t ckmin (idd); cs is high; address and command inputs are switching; data i/o are switch- ing; output buffer (dq, dqs) is off (mr1 bit a12 = 1); rtt_nom and rtt_wr are disabled; all banks active. i dd4r operating current burst read cke is high; external clock is on; t ck = t ckmin (idd); cl = cl(idd); cs is high between valid commands; command inputs are switching except during read commands; column addresses are switching; address input a10 must be low at all times; bank addresses are cycling (0 1 2 3); data i/o use seamless read data burst (bl8); output buffer (dq, dqs) is off (mr1 bit a12 = 1) in order to achieve i out = 0ma; rtt_nom and rtt_wr are disabled; burst length = 8 fixed (mr0 bits [a1,a0] = {0,0}); all banks active. i dd4w operating current burst write cke is high; external clock is on; t ck = t ckmin (idd); cl = cl(idd); cs is high between valid commands; command inputs are switching except during write commands; column addresses are switching; address input a10 must be low at all times; bank addresses are cycling (0 1 2 3); data i/o use seamless write data burst (bl8); output buffer (dq, dqs) is off (mr1 bit a12 = 1) in order to achieve i out = 0ma; rtt_nom and rtt_wr are disabled; burst length = 8 fixed (mr0 bits [a1,a0] = {0,0}); all banks active. i dd5b burst refresh current cke is high; external clock is on; t ck = t ckmin (idd); t rfc = t rfc- min (idd); cs is high between valid commands; address and command inputs are switching; data i/o are switching; output buffer (dq, dqs) is off (mr1 bit a12 = 1); rtt_nom and rtt_wr are disabled; refresh command every t rfc = t rfcmin . i dd6 self-refresh current normal temperature range t case = 0 to 85c t case = 85c; normal temperature range (mr2 bit a6 = 0); cke is low; external clock is off; ck/ck are low; cs is floating; com- mand inputs are floating; row and column addresses are float- ing; bank addresses are floating; data i/o are floating; output buffer (dq, dqs) is off (mr1 bit a12 = 1); rtt_nom and rtt_wr are dis- abled; all banks are active during self-refresh actions; all banks are idle between self-refresh actions.
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 26 idd measurement conditions (contd.) notes: 1. the mr0 bit a12 defines dll on/off behavior only for precharge power down. there are 2 different precharge power down states possible: one with dll on (fast exit, bit 12 = 1) and one with dll off (slow exit, bit 12 = 0). 2. because it is an exit after precharge power down, the valid commands are: activate, refresh, mode-register set, enter - self refresh. 3. ddr3 will offer only one active power down mode with dll on ( fast exit). mr0 bit a12 will not be used for active power down. instead bit a12 will be used to switch between two different precharge power down modes. symbol description conditions i dd6et self-refresh current extended temperature range t case = 85 to 95c t case = 95c; extended temperature range (mr2 bit a6 = 1); cke is low; external clock is off; ck/ck are low; cs is floating; com- mand inputs are floating; row and column addresses are float- ing; bank addresses are floating; data i/o are floating; output buffer (dq, dqs) is off (mr1 bit a12 = 1); rtt_nom and rtt_wr are dis- abled; all banks are active during self-refresh actions; all banks are idle between self-refresh actions. i dd7 all bank interleave read current cke is high; external clock is on; t ck = t ckmin (idd); t rc = t rcmin (idd); t ras = t rasmin (idd); t rcd = t rcdmin (idd); t rrd = t rrdmin (idd); cl = cl(idd); al = t rcdmin - 1 * t ck ; cs is high between valid commands; for command inputs, see device datasheet for test patterns; row and column addresses are stable during deselects; bank addresses are cycling (0 1 2 3); data i/o use read data (bl8); dm is low at all times; output buffer (dq, dqs) is off (mr1 bit a12 = 1) in order to achieve i out = 0ma; rtt_nom and rtt_wr are disabled; burst length = 8 fixed (mr0 bits [a1,a0] = {0,0}); all banks active (rotational).
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 27 idd specifications speed bin ddr3-1333 units notes parameter 9-9-9 i dd0 2045 ma i dd1 2225 ma i dd2p (0) 866 ma i dd2p (1) 1550 ma i dd2n 1730 ma i dd2q 1730 ma i dd3p 1685 ma i dd3n 1820 ma i dd4r 3080 ma i dd4w 3305 ma i dd5b 3215 ma i dd6 180 ma i dd6et tbd ma i dd7 4520 ma
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 28 refresh parameters parameter symbol 1gb units ref command to act or ref command time t rfc 110 ns average periodic refresh interval 0 c t case 85 c t refi 7.8 s 85 c t case 95 c 3.9 s device standard speed bins speed bin ddr3-1333 units notes cl - nrcd - nrp 9-9-9 parameter symbol min max internal read command to first data t aa 13.5 20 ns act to internal read or write delay time t rcd 13.5 - ns pre command period t rp 13.5 - ns act to act or ref command period t rc 49.5 - ns act to pre command period t ras 36 9 * t refi ns cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3, 5 cwl = 6, 7 reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 1.875 < 2.5 ns 1, 2, 3, 5 cwl = 7 reserved ns 4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 1.5 < 1.875 ns 1, 2, 3 supported cl settings 6, 8, 9 n ck supported cwl settings 5, 6, 7 n ck
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 29 speed bin tables notes 1. the cl setting and cwl setting result in t ck(avg) min and t ck(avg) max requirements. when making a selec- tion of t ck(avg) , both need to be fulfilled: requirements from cl setting as well as requirements from cwl setting. 2. t ck(avg) min limits: since cas latency is not purely analog - data and strobe output are synchronized by the dll - all possible intermediate frequencies may not be guaranteed. an application should use the next smaller jedec standard t ck(avg) value (2.5, 1.875, or 1.5) when calculating cl [nck] = t aa [ns] / t ck(avg) [ns], rounding up to the next ?supported cl?. 3. t ck(avg) max limits: calculate t ck(avg) = t aa max / cl selected and round the resulting t ck(avg) down to the next valid speed bin (i.e. 3.3ns, 2.5ns, or 1.875 ns). this result is t ck(avg) max corresponding to cl selected. 4. ?reserved? settings are not allowed. user must program a different value. 5. any ddr3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization.
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 30 device timing parameters by speed bin parameter symbol ddr3-1333 units notes min max clock timing minimum clock cycle time (dll off mode) t ck(dll_off) 8- t ck 6 average clock period t ck(avg) refer to speed bin on page 28 ps average high pulse width t ch(avg) 0.47 0.53 t ck(avg) average low pulse width t cl(avg) 0.47 0.53 t ck(avg) absolute clock period t ck(abs) t ck(avg)min + t jit(per)min t ck(avg)max + t jit(per)max ps absolute clock high pulse width t ch(abs) 0.43 - t ck(avg) 25 absolute clock low pulse width t cl(abs) 0.43 - t ck(avg) 26 clock period jitter t jit(per) -80 80 ps clock period jitter during dll locking period t jit(per, lck) -70 70 ps cycle to cycle period jitter t jit(cc) 160 ps cycle to cycle period jitter during dll locking period t jit(cc, lck) 140 ps duty cycle jitter t jit(duty) --ps cumulative error across 2 cycles t err(2per) -118 118 ps cumulative error across 3 cycles t err(3per) -140 140 ps cumulative error across 4 cycles t err(4per) -155 155 ps cumulative error across 5 cycles t err(5per) -168 168 ps cumulative error across 6 cycles t err(6per) -177 177 ps cumulative error across 7 cycles t err(7per) -186 186 ps cumulative error across 8 cycles t err(8per) -193 193 ps cumulative error across 9 cycles t err(9per) -200 200 ps cumulative error across 10 cycles t err(10per) -205 205 ps cumulative error across 11 cycles t err(11per) -210 210 ps cumulative error across 12 cycles t err(12per) -215 215 ps cumulative error across n = 13-50 cycles t err(nper) t err(nper)min = (1 + 0.68ln(n)) * t jit(per)min t err(nper)max = (1 + 0.68ln(n)) * t jit(per)max ps 24
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 31 device timing parameters by speed bin (contd.) parameter symbol ddr3-1333 units notes min max data timing dqs, dqs to dq skew, per group, per access t dqsq - 125 ps 13 dq output hold time from dqs, dqs t qh 0.38 - t ck(avg) 13, b dq low-impedance from ck, ck t lz(dq) -500 250 ps 13, 14, a dq high-impedance from ck, ck t hz(dq) - 250 ps 13, 14, a data setup time to dqs, dqs referenced to v ih(ac) / v il(ac) levels t ds(base) tbd - ps 17, d data hold time from dqs, dqs referenced to v ih(dc) / v il(dc) levels t dh(base) tbd - ps 17, d data strobe timing dqs, dqs differential read preamble t rpre 0.9 note 19 t ck(avg) 13, 19, b dqs, dqs differential read postamble t rpst 0.3 note 11 t ck(avg) 11, 13, b dqs, dqs differential output high time t qsh 0.4 - t ck(avg) 13, b dqs, dqs differential output low time t qsl 0.4 - t ck(avg) 13, b dqs, dqs differential write preamble t wpre 0.9 - t ck(avg) dqs, dqs differential write postamble t wpst 0.3 - t ck(avg) dqs, dqs rising edge output access time from rising ck, ck t dqsck -255 255 ps 13, a dqs and dqs low-impedance time (referenced from rl - 1) t lz(dqs) -500 250 ps 13, 14, a dqs and dqs low-impedance time (referenced from rl + bl / 2) t hz(dqs) - 250 ps 13, 14, a dqs, dqs differential input low pulse width t dqsl 0.4 0.6 t ck(avg) dqs, dqs differential input high pulse width t dqsh 0.4 0.6 t ck(avg) dqs, dqs rising edge to ck, ck rising edge t dqss -0.25 0.25 t ck(avg) c dqs, dqs falling edge setup time to ck, ck rising edge t dss 0.2 - t ck(avg) c dqs, dqs falling edge hold time from ck, ck rising edge t dsh 0.2 - t ck(avg) c
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 32 device timing parameters by speed bin (contd.) parameter symbol ddr3-1333 units notes min max command and address timing dll locking time t dllk 512 - nck internal read command to precharge command delay t rtp max (4nck, 7.5ns) -e delay from start of internal write transaction to internal read command t wtr max (4nck, 7.5ns) - 18, e write recovery time t wr 15 - ns e mode register set command cycle time t mrd 4-nck mode register set command update delay t mod max (12nck, 15ns) - act to internal read or write delay time t rcd refer to speed bin on page 28 e precharge command period t rp refer to speed bin on page 28 e act to act or ref command period t rc refer to speed bin on page 28 e cas to cas command delay t ccd 4-nck auto-precharge write recovery + precharge time t dal(min) wr + roundup (t rp / t ck(avg) ) nck multi-purpose register recovery time t mprr 1-nck22 active to precharge command period t ras refer to speed bin on page 28 e active to active command period for 1kb page size t rrd max (4nck, 6ns) -e four activate window for 1kb page size t faw 30 - ns e command and address setup time to ck, ck referenced to v ih(ac) / v il(ac) levels t is(base) 65 - ps 16, b command and address hold time to ck, ck referenced to v ih(dc) / v il(dc) levels t ih(base) 140 - ps 16, b command and address setup time to ck, ck referenced to v ih(ac) / v il(ac) levels t is(base) ac150 65 + 125 - ps 16, 27, b calibration timing power-up and reset calibration time t zqinit 512 - nck normal operation full calibration time t zqoper 256 - nck normal operation short calibration time t zqcs 64 - nck 23
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 33 device timing parameters by speed bin (contd.) parameter symbol ddr3-1333 units notes min max reset timing exit reset from cke hich to a valid com- mand t xpr max (5nck, t rfc (min) + 10ns) - self refresh timing exit self refresh from to commands not requiring a locked dll t xs max (5nck, t rfc (min) + 10ns) - exit self refresh from to commands requir- ing a locked dll t xsdll t dllk (min) -nck minimum cke low width for self refresh entry to exit timing t ckesr t cke (min) + 1nck - valid clock requirement after self refresh entry (sre) or power-down entry (pde) t cksre max (5nck, 10ns) - valid clock requirement before self refresh exit (srx) or power-down exit (pdx) or reset exit t cksrx max (5nck, 10ns) - power down timing exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll t xp max (3nck, 7.5ns) - exit precharge power down with dll frozen to commands requiring a locked dll t xpdll max (10nck, 24ns) -2 command pass disable delay t cpded 1-nck power down entry to exit timing t pd t cke (min) 9 * t refi 15 timing of act command to power down entry t actpden 1-nck20 timing of pre or prea command to power down entry t prpden 1-nck20 timing of rd/rda command to power down entry t rdpden rl + 4 + 1 - nck cke minimum pulse width t cke max (3nck, 5.625ns) -nck
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 34 device timing parameters by speed bin (contd.) parameter symbol ddr3-1333 units notes min max timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) t wrpden wl + 4 + (t wr / t ck(avg) ) -nck9 timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) t wrapden wl + 4 + wr + 1 -nck10 timing of wr command to power down entry (bc4mrs) t wrpden wl + 2 + (t wr / t ck(avg) ) -nck9 timing of wra command to power down entry (bc4mrs) t wrapden wl +2 + wr + 1 - nck 10 timing of ref command to power down entry t refpden 1 - nck 20, 21 timing of mrs command to power down entry t mrspden t mod (min) - odt timing odt high time without write command or with write command and bc4 odth4 4 - nck odt high time with write command and bl8 odth8 6 - nck asynchronous rtt turn-on delay (power- down with dll frozen) t aonpd 19ns asynchronous rtt turn-off delay (power- down with dll frozen) t aofpd 19ns rtt turn-on t aon -250 250 ps 7, a rtt_nom and rtt_wr turn-off time from odtloff reference t aof 0.3 0.7 t ck(avg) 8, a rtt dynamic change skew t adc 0.3 0.7 t ck(avg) a write leveling timing first dqs/dqs rising edge after write leveling mode is programmed t wlmrd 40 - nck 3 dqs/dqs delay after write leveling mode is programmed t wldqsen 25 - nck 3 write leveling setup time from rising ck, ck crossing to rising dqs, dqs crossing t wls 195 - ps write leveling hold time from rising dqs, dqs crossing to rising ck, ck crossing t wlh 195 - ps write leveling output delay t wlo 09ns write leveling output error t wloe 02ns
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 35 device timing parameters notes 1. actual value dependant upon measurement level definitions which are tbd. 2. commands requiring a locked dll are: read (and rap) and synchronous odt commands. 3. the max values are system dependent. 4. wr as programmed in the mode register. 5. value must be rounded-up to next higher integer value. 6. there is no maximum cycle time limit besides the need to satisfy the refresh interval, t refi . 7. minimum rtt turn-on time ( t aonmin) is the point in time when the device leaves high impedance and odt resistance begins to turn on. maximum rtt turn on time ( t aonmax) is the point in time when the odt resist ance is fully on. both are measured from odtlon. 8. minimum rtt turn-off time ( t aofmin) is the point in time when the device starts to turn off the odt resistance. maximum rtt turn off time ( t aofmax) is the point in time when the on-die termination has reached high impedance. both are measured from odtloff. 9. t wr is defined in ns, for calculation of t wrpden it is necessary to round up t wr / t ck to the next integer. 10. wr is in clock cycles as programmed in mr0. 11. the maximum postamble is bound by t hzdqs (max) 12. output timing deratings are relative to the sdram input cl ock. when the device is operated with input clock jitter, this par ameter needs to be derated by tbd. 13. value is only valid for ron34 14. single ended signal parameter. 15. t refi depends on t oper . 16. t is(base) and t ih(base) values are for 1v/ns cmd/add single-ended slew rate and 2v/ns ck, ck differential slew rate. note for dq and dm signals, v ref(dc) = v refdq(dc) . for input only pins except reset , v ref(dc) = v refca(dc) . 17. t ds(base) and t dh(base) values are for 1v/ns dq single-ended slew rate and 2v/ns dqs, dqs differential slew rate. note for dq and dm signals, v ref(dc) = v refdq(dc) . for input only pins except reset , v ref(dc) = v refca(dc) . 18. start of internal write transaction is defined as follows: for bl8 (fixed by mrs and on- the-fly): rising clock edge 4 clock cycles after wl. for bc4 (on- the- fly): rising clock edge 4 clock cycles after wl. for bc4 (fixed by mrs): rising clock edge 2 clock cycles after wl. 19. the maximum preamble is bound by t lzdqs (min). 20. cke is allowed to be registered low while operations such as row activation, precharge, autop recharge or refresh are in prog ress, but power-down idd spec will not be appl ied until finishing those operations. 21. although cke is allowed to be registered low after a refresh command once t refpden (min) is satisfied, there are cases where addi- tional time such as t xpdll (min) is also required. 22. defined between end of mpr read burst and mrs wh ich reloads mpr or disables mpr function. 23. one zqcs command can effectively correct a minimum of 0.5% (zqcorrection) of ron and rtt impedance error within 64 nck for a ll speed bins assuming the maximum sensitivities specified in the ?output driver voltage and temperature sensitivity? and ?odt vol tage and temperature sensitivity? tables. the appropr iate interval between zqcs commands can be determined from these tables and other a ppli- cation-specific parameters. one method for calculating the interval between zqcs commands, given the temperature (tdriftrate) and voltage (vdriftrate) drif t rates that the sdram is subject to in the application, is illust rated. the interval could be defined by the following formula: where tsens = max(drttdt, drondtm) and vsens = max(drttdv, drondvm) define the sdram temperature and voltage sensitivi- ties. for example, if tsens = 1.5% / c, vsens = 0.15% / mv, tdriftrate = 1 c / sec and vdriftrate = 15 mv / sec, then the interval between zqcs commands is calculated as: 24. n = from 13 cycles to 50 cycles. this row defines 38 parameters. 25. t ch(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. 26. t cl(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge. 27. the t is(base) ac150 specifications are adjusted from the t is(base) specification by adding an additional 100 ps of derating to accommodate for the lower alternate threshold of 150 mv and another 25 ps to account for the earlier reference point [(175 mv - 150 mv) / 1 v/ns]. zqcorrection tsens tdriftrate () vsens tvdriftrate () + ---------------------------------------------------------------------------------------------------------------------------- - 0.5 1.5 1 () 0.15 15 + () + ------------------------------------------------------- 0 . 1 3 3 1 2 8 ms =
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 36 jitter notes a when the device is operated with input clock jitter, this parameter needs to be derated by the actual t err(mper) act of the input clock, where 2 m 12. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr3-800 sdram has t err(mper) act,min = - 172 ps and t err(mper) act,max = + 193 ps, then t dqsck min(derated) = t dqsck min - t err(mper) act,max = - 400 ps - 193 ps = - 593 ps and t dqsck max(derated) = t dqsck ,max - t err(mper) act,min = 400 ps + 172 ps = + 572 ps. similarly, t lz(dq) for ddr3-800 derates to t lz(dq) min(derated) = - 800 ps - 193 ps = - 993 ps and t lz(dq) max(derated) = 400 ps + 172 ps = + 572 ps. (caution on the min/max usage!) note that t err(mper) act,min is the minimum measured value of t err(nper) where 2 n 12, and t err(mper) act,max is the maximum mea- sured value of t err(nper) where 2 n 12. b when the device is operated with input clock jitter, this parameter needs to be derated by the actual t jit(per) ,act of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr3-800 sdram has t ck(avg) act = 2500 ps, t jit(per) act,min = - 72 ps and t jit(per) act,max = + 93 ps, then t rpre min(derated) = t rpre min + t jit(per) act,min = 0.9 x t ck(avg) act + t jit(per) act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. similarly, t qh min(derated) = t qh min + t jit(per) act,min = 0.38 x t ck(avg) act + t jit(per) act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (caution on the min/max usage!) c these parameters are measured from a data strobe signal (dqs, dqs ) crossing to its respective clock signal (ck, ck ) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as these are relative to the cl ock signal crossing. that is, these parameters should be met w hether clock jitter is present or not. d these parameters are measured from a data signal (dm, dq0, dq1, etc.) transition edge to its respective data strobe signal (dq s, dqs ) crossing. e for these parameters, the ddr3 sdram device supports t nparam [nck] = ru{t param [ns] / t ck(avg) [ns]}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. for example, the device will support t nrp = ru{t rp / t ck(avg) }, which is in clock cycles, if all input clock jitter specifications ar e met. this means: for ddr3-800 6-6-6, of which t rp = 15ns, the device will support t nrp = ru{t rp / t ck(avg) } = 6, as long as the input clock jitter specifications are met, i.e. precharge command at tm and active command at tm+6 is valid even if (tm+6 - tm) is less than 15 ns due to input clock jitter.
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 37 part number decode 1 smart modular technologies 2 module process technology g: green module (rohs compliant) 3 module address depth 256: 256m 4 module data bus width 7: x72 5 module configuration rd3: ddr3 registered dimm 6 device configuration 128: 128mx8 7 cas latency 9: cl 9.0 8 module speed 3: ddr3-1333 9 device vendor h: hynix s: samsung 10 device revision b: revision b d: revision d e: revision e 11 register d: idt register s g 256 7 rd3 128 9 3 u u d 12 3 4 5 6 7891011 note: ?u? in the part number should be replaced by user specified option.
SG2567RD312893UUD february 20, 2009 corporate headquarters: p. o. box 1757, fremont, ca 94538, usa ? tel:(510) 623-1231 ? fax:(510) 623-1434 ? e-mail: info@smartm.com europe: 5 kelvin park south, kelvin south, east kilbride, g75 orh, united kingdom ? tel: +44-870-870-8747 ? fax: +44-870-870-8757 asia/pacific: plot 18, lrg jelawat 4, kawasan perindustrian seberang jaya 13700, prai, penang, malaysia ? tel: +604-3992909 ? fax: +604-3992 903 38 disclaimer: no part of this document may be copied or reproduced in any form or by any means, or transferred to any third party, without the prior written consent of an authorized representative of smart modular technologies, inc. (?smart?). the information in this document is subject to change without notice. smart assumes no responsibil- ity for any errors or omissions that may appear in this document, and disclaims responsibility for any conse- quences resulting from the use of the information set forth herein. smart makes no commitments to update or to keep current information contained in this document. the products listed in this document are not suitable for use in applications such as, but not limited to, aircraft control systems, aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. moreover, smart does not recommend or approve the use of any of its products in life support devices or systems or in any application where failure could result in injury or death. if a customer wishes to use smart products in applications not intended by smart, said customer must contact an authorized smart representative to determine smart?s willingness to support a given application. the information set forth in this document does not convey any license under the copyrights, patent rights, trade- marks or other intellectual property rights claimed and owned by smart. the information set forth in this docu- ment is considered to be ?proprietary? and ?confidential? property owned by smart. all products sold by smart are covered by th e provisions appearing in smart?s terms and conditions of sale only, including the limitations of liability, warranty and infringement provisions. smart makes no warranties of any kind, express, statutory, implied or otherwise, regarding informatio n set forth herein or regarding the free- dom of the described products from intellectual property infringement, and expressly disclaims any such warranties including without limitation any express, statutory or implied warranties of merchantability or fitness for a particular pur- pose. ?1996 smart modular technologies, inc. all rights reserved.

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